1. Field of the Invention
The present invention generally relates to the forming of integrated circuits on a silicon substrate. More specifically, the present invention relates to the forming of localized regions of a material difficult to etch. “Difficult to etch” means in the present description a lack of etch selectivity with respect to the materials used in the standard silicon circuit manufacturing process, or the fact that the usable chemicals would be polluting for the other integrated circuit elements.
Such materials are, for example, materials with a high dielectric permittivity intended to form the inter-electrode insulator of a capacitive element or a MOS transistor gate insulator. “Materials with a high dielectric permittivity” is used to designate in the present description insulators with a dielectric permittivity up to from one hundred to one thousand times greater than that of silicon oxide (SiO2). Among such insulators, metal oxides of type MO2, MSixOy, or MAlxOy, where x and y designate integers and M a metal atom selected from among the group comprising hafnium, zirconium, lanthanum, and aluminum can be found.
More specifically, the present invention relates to the forming of such elements comprising an insulator of high dielectric permittivity.
2. Discussion of the Related Art
FIGS. 1A and 1B illustrate, in a simplified partial cross-section view, successive steps of the forming of an insulated gate of a MOS transistor according to another known method.
As illustrated in FIG. 1A, a thin layer of an insulator 2, followed by a conductive layer 3, are successively deposited on a semiconductor substrate 1, typically silicon.
Then, as illustrated in FIG. 1B, an insulated gate 4 is defined by etching the stacking of insulator 2 and of conductive layer 3. Insulator 2 typically is a silicon oxide (SiO2) resulting either from a chemical vapor deposition (CVD), or from a thermal oxidation of the surface of substrate 1. Conductive layer 3, intended to form the gate electrode, generally is polysilicon.
In modern technologies, the gate lengths are more and more reduced, and the thickness of insulator 2 must be reduced. However, it is not possible, for physical reasons, to reduce the thickness of an insulator beyond a given limit on the order of 1.5 nm. This limits the possibility of reduction of the gate electrode dimensions.
To enable additional reduction of dimensions, it has been attempted to use as an insulator 2 insulating materials with a high dielectric permittivity. However, such insulators are difficult to etch. To avoid any etching, it has been devised to implement a method of damascene type.
FIG. 2 illustrates, in a partial simplified cross-section view, an intermediary step of a damascene method. Such a method consists of repeating, for each insulating or conductive element 2 intended to form the insulated gate, the succession of steps consisting of depositing an insulating layer, opening it according to the gate contour, depositing the layer of the material difficult to etch, and leveling the surface, generally by chem.-mech polishing (CMP). The structure thus obtained is illustrated in FIG. 2, in which reference numeral 21 designates a first insulator, reference numeral 2 designates the gate insulator difficult to etch, reference 22 designates a second insulator, and reference 3 designates the gate conductor. Then, to obtain the structure illustrated in FIG. 1B, insulators 21 and 22 are selectively removed.
This method has several disadvantages. Especially, insulating layers, one at least of which usually is silicon nitride, are used as intermediary layers 21, 22. The silicon nitride imposes on underlying substrate 1 mechanical constraints such that its crystal structure is deformed. This alters the performance, not only of the formed capacitive element, but also of the neighboring devices. In particular, in the case of the forming of a transistor, the doping profiles of the channel and of the subsequently-formed source/drain regions are affected.
Similar problems are encountered upon integration of any capacitive element comprising as an inter-electrode insulator an insulator of high dielectric permittivity.